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Looking for materials about low power ASIC RTL

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shitansh

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Hi,

can any one provide some material or docs related to low power ASIC RTL design.

In my need, i need to work on the low power RTL design where, I need to instantiate some power domain crossing cells in the existing RTL and have to write a constrain file for VCS (synopsis simulation tool) for doing the proper verification of these cells.

Waiting for your reply,
Thanks,
Shitansh Vaghela
 

cvc

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Re: low power ASIC RTL

shitansh said:
Hi,

can any one provide some material or docs related to low power ASIC RTL design.

In my need, i need to work on the low power RTL design where, I need to instantiate some power domain crossing cells in the existing RTL and have to write a constrain file for VCS (synopsis simulation tool) for doing the proper verification of these cells.

Waiting for your reply,
Thanks,
Shitansh Vaghela

Basically you need to be writing UPF/CPF files and mention your PDs. The tweak your stimulus to model the Power State Table. You may also add assertions to verify the Power Management Unit (PMU) and func-cov to ensure full testing.

During previous academic year, Sugnath Kumar, a M.Tech VLSI graduate from Amrita Engg college Bangalore worked on similar project with us at CVC (www.cvcblr.com) as his Master's thesis. This was part of our BUDS Internship, a free - Do-it Yourself Internship with guidance from TeamCVC - see: https://www.cvcblr.com/downloads/BUDs_CVC_Acad.pdf

If you are a current final year student, contact us via www.cvcblr.com for more on this. You may also contact Suganth directly via: https://in.linkedin.com/pub/suganth-kumar/1b/2a2/11

We are also publishing a paper based on this work at VLSI COnf 2011 (if accepted, of-course).

Regards
TeamCVC
www.cvcblr.com/blog
 

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