Looking for LCD model to verify LCD controller in Verilog

[handsome]

help:about lcd model

I have design a lcd controller in verilog. Now I want to verify it, so I need a lcd model which my lcd controller can work with. And the lcd model should display the picture which will help me to verify the lcd controller’s performance. Where can I get such a model? Can you tell me ? Do you have a better way to verify my lcdc? THx!

 

[CRiSP]

Re: help:about lcd model

I have design a lcd controller in verilog. Now I want to verify it, so I need a lcd model which my lcd controller can work with. And the lcd model should display the picture which will help me to verify the lcd controller’s performance. Where can I get such a model? Can you tell me ? Do you have a better way to verify my lcdc? THx!

hv u LCD Driver analog part?

 

[handsome]

Re: help:about lcd model

No. I only design a Lcd controller. The analog driver is not included.

 

[realtek]

Re: help:about lcd model

depende on which waveform your lcd controller need
without driver
you can only simulate the the waveform whuch driver can recept
but cannot show a picture
maybe use FPGA + Driver IC is the best way to verify your code
if not. you need write the model by yourself
otherwise nobody know what kind signal you need!

 

[balik]

help:about lcd model

it is really better to check controller in FPGA first
especially if you want to use dithering for STN because in this case it is important not only waveform but algorithm of dithering too

 

[handsome]

Re: help:about lcd model

Ok ,now I have developed a evaluation board to evaluate my lcd controller. I will give up design a lcd model.
About a month ago, I heard from a person who told me I can find a lcd panel model to verify my design .The lcd panel model is written in C or such other high level language and it can link to simulator through PLI, and it can communicate with Solaris through win32 program ,then it can display the picture.
To balik : I do design a STN lcd controller . but I think the dithering algorithms or FRC is internal algorithms ,and my lcd controller’s interface is compatible with most lcd panel , the interface signal is ld[15:0] , sclk, lp, flm, acd .

 

[lyu]

Re: help:about lcd model

in this design , have you consider the "horizontal timing restrictions"?
Some time must be allowed for the DMA transfer and for the data to propagate down the FIFO path in the LCD interface. The data path laency forces some restrictions on the usable minimum values for horizontal porch width in STN mode.
can you give me some details about it ?