hunter
Newbie level 4
job hunting
Hi, all
I know it's not a right place to post, sorry for any inconvenience.
For some reason, a SR. ASIC Design engineer is looking for an ASIC Design opptunity. currently I live in Silicon Valley,ca,US. have almost ten chips successfully tape-outs(under .18, timing critical) including some big chips came from big company, such as yamaha, ubicom, toshiba etc. Focusing on back-end,took charge of P&R,verification,Power Analysis, timng closure, foundry interface. very good person to challenge the timing critical, multi-million designs. cause I used to be front-end designer. Apollo/SoCEncounter are as the main P&R tools.
details according to some of my chips:
dsp: 600K,330M, 0.13um,
risc cpu: 400K,300M, 0.18um.
network chip: 500K,250M, 0.15LV.
network chip: 5M, 240M, 0.13um,12clock domains, 6power domains.
SOC chip: 5M, 200M, 0.13u, (ongoing)
any information will be highly appreciated.
Hi, all
I know it's not a right place to post, sorry for any inconvenience.
For some reason, a SR. ASIC Design engineer is looking for an ASIC Design opptunity. currently I live in Silicon Valley,ca,US. have almost ten chips successfully tape-outs(under .18, timing critical) including some big chips came from big company, such as yamaha, ubicom, toshiba etc. Focusing on back-end,took charge of P&R,verification,Power Analysis, timng closure, foundry interface. very good person to challenge the timing critical, multi-million designs. cause I used to be front-end designer. Apollo/SoCEncounter are as the main P&R tools.
details according to some of my chips:
dsp: 600K,330M, 0.13um,
risc cpu: 400K,300M, 0.18um.
network chip: 500K,250M, 0.15LV.
network chip: 5M, 240M, 0.13um,12clock domains, 6power domains.
SOC chip: 5M, 200M, 0.13u, (ongoing)
any information will be highly appreciated.