mchieco
Newbie
Project Overview
We are a startup developing microchiplet-based electronics, a novel approach to modular microelectronic systems. To validate our process, we need a test microchiplet designed with a focus on low-cost fabrication and rapid iteration.
This will be a small-scale, minimal transistor-count design to be fabricated on an MPW (multi-project wafer) run. The primary goal is to validate microchiplet singulation, interconnects, and basic logic functions.
What We Need
We need an experienced IC designer (analog/mixed-signal or digital) to help with:
Schematic capture and RTL design (simple logic, SRAM, and a basic sensor)
Layout design & DRC/LVS sign-off (90nm or 130nm node, FD-SOI process preferred)
I/O pad placement (TSVs or alternative interconnect methods)
Optimizing for MPW manufacturability
Chiplet Specs
Process: FD-SOI (90nm or 130nm preferred)
Size: 25-50µm diameter circular die
Transistor Budget: ~1,000-5,000
Functions: Simple ALU (compute), small SRAM block (memory), temperature sensor (sensing)
I/O: TSVs or traditional wirebondable pads
Who Should Apply?
IC designers experienced in low-power, small-scale ASICs
Familiarity with MPW processes (Efabless, Europractice, SkyWater, etc.)
Experience with open-source EDA tools (Magic VLSI, OpenROAD, KLayout, etc.) a plus
Ability to deliver GDS-II, netlist, and layout documentation
We are a startup developing microchiplet-based electronics, a novel approach to modular microelectronic systems. To validate our process, we need a test microchiplet designed with a focus on low-cost fabrication and rapid iteration.
This will be a small-scale, minimal transistor-count design to be fabricated on an MPW (multi-project wafer) run. The primary goal is to validate microchiplet singulation, interconnects, and basic logic functions.
What We Need
We need an experienced IC designer (analog/mixed-signal or digital) to help with:
Schematic capture and RTL design (simple logic, SRAM, and a basic sensor) Layout design & DRC/LVS sign-off (90nm or 130nm node, FD-SOI process preferred) I/O pad placement (TSVs or alternative interconnect methods) Optimizing for MPW manufacturabilityChiplet Specs
Process: FD-SOI (90nm or 130nm preferred)
Size: 25-50µm diameter circular die
Transistor Budget: ~1,000-5,000
Functions: Simple ALU (compute), small SRAM block (memory), temperature sensor (sensing)
I/O: TSVs or traditional wirebondable pads
Who Should Apply?
IC designers experienced in low-power, small-scale ASICs Familiarity with MPW processes (Efabless, Europractice, SkyWater, etc.) Experience with open-source EDA tools (Magic VLSI, OpenROAD, KLayout, etc.) a plus Ability to deliver GDS-II, netlist, and layout documentation