weng
Member level 1
I need to have a logic to detect ONLY 1 bit high in a bus.
For example:
a bus signal Y[3:0]. output OUT High only if Y == 0001 or Y == 0010 or Y == 0100 or Y == 1000.
What is the best way to code it in Verilog? In terms of min gate transition?
For example:
a bus signal Y[3:0]. output OUT High only if Y == 0001 or Y == 0010 or Y == 0100 or Y == 1000.
What is the best way to code it in Verilog? In terms of min gate transition?