logic to detect 1 bit (only 1 bit) High in a bus

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weng

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I need to have a logic to detect ONLY 1 bit high in a bus.

For example:
a bus signal Y[3:0]. output OUT High only if Y == 0001 or Y == 0010 or Y == 0100 or Y == 1000.

What is the best way to code it in Verilog? In terms of min gate transition?
 

time as well as area optimize circuit will be a combinational circuit as follows
consider your bus is n bit in width then u need 'n' no of n-input NAND gate and one n-input OR gate and n no of NOT gates.
logic is simple , each NAND will detect a sequence containning one logic one . like wise there will be n sequence having singe one on it and therefore n nos of NAND gates. out put of all NAND will be given to OR.
 

depending how wide your bus is, but I would try to use FA (full adders).
this is not true addition logic since once you have a carry in one of the FA you can immediately bypass the result to the output, since it means you got more than 1 "1".
In some cases this would be faster and for sure less area (and power) than the fully paralleled approach.

ND.
https://asicdigitaldesign.wordpress.com
 

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