the question is not very clear.... the RTL_Compiler will first convert the design into gates... then the tool will try to optimize the gates to meet the timing...like a mux can be used or AOI gate to implement a mux_functionality to meet the timing .... this is done in a simplistic way because you don't have parasitics.....
this optimization goes on at every stage of the design : Placement/CTS/Post route etc....
Nice to see that you are asking some very fundamental questions. To get proper and elaborate answers I would suggest (again) you to refer to the RC documentation or read some research papers on how EDA tools (in your case synthesis tools) function. You have to understand the algorithm/s the synthesis tools are using.