logic synthesis optimization

[dha_synth]

hello all,

In RTL compiler while synthesis, at the time of elaboration tool optimize mux and the datapath.

Can anyone please explain in detail.


Thanx in edvance
dha_synth

 

[artmalik]

the question is not very clear.... the RTL_Compiler will first convert the design into gates... then the tool will try to optimize the gates to meet the timing...like a mux can be used or AOI gate to implement a mux_functionality to meet the timing .... this is done in a simplistic way because you don't have parasitics.....
this optimization goes on at every stage of the design : Placement/CTS/Post route etc....

 

[D.A.(Tony)Stewart]

**broken link removed**

 

[dha_synth]

dear artmalik,
thanks for the reply.
Actually my question is how SOP and POS are used to optimize area and speed of the design.

Kindly help

 

[dha_synth]

dear artmalik,
thanks for the reply.
Actually my question is how SOP and POS are used to optimize area and speed of the design.

Kindly help

 

[dpaul]

Nice to see that you are asking some very fundamental questions. To get proper and elaborate answers I would suggest (again) you to refer to the RC documentation or read some research papers on how EDA tools (in your case synthesis tools) function. You have to understand the algorithm/s the synthesis tools are using.

I Googled the phrase "SOP and POS are used to optimize area and speed of the design" and came up with the following which might me useful.
www.eecs.berkeley.edu/~alanmi/publications/2011/iccad11_sop.pdf
cas.ee.ic.ac.uk/people/gac1/pubs/TheoDATE11.pdf

Always remember that Google is your 1st best friend!