alokem
Newbie level 6
Hi ,
how to reduce high logic levels (present in datapath blocks) duirng synthesis using design compiler through better optimization ? I need proper attrbutes / any other way which can be used during synthesis so that logic level can be reduced .
how to reduce high logic levels (present in datapath blocks) duirng synthesis using design compiler through better optimization ? I need proper attrbutes / any other way which can be used during synthesis so that logic level can be reduced .