frankqt
Member level 4
I need help from the masters here. I took a project without fully understanding the implications and now I am out of time and need some expert guidance.
I am building a hardware for a complex application. I understand the overall system well however I have zero FPGA experience. I am in the process of selecting a low cost FPGA for the app.
In the app FPGA acts as a data pipe. I have two cameras, they have standard 10 bit interfaces (D0-9, Fsynch, Lsynch, CLK). Cams take video and FPGA sucks the data out and write to a 256Mbyte RAM. CAMs are taking images simultaneously but they are not synchronized. The data may come at the same time or some time apart. FPGA writes each cam's data in a different place in RAM. Once the video taking is finished, it sends the data via SPI to CPU. That's pretty much it.
I am trying to see what would be the estimated LEs for something like this. I am choosing the Cyclone IV E series with 6K LEs. Is 6K LE enough? In this 6K, I would have to implement SPI, SDRAM and 2 camera interfaces and a few registers for CPU to coordinate operation.
I am building a hardware for a complex application. I understand the overall system well however I have zero FPGA experience. I am in the process of selecting a low cost FPGA for the app.
In the app FPGA acts as a data pipe. I have two cameras, they have standard 10 bit interfaces (D0-9, Fsynch, Lsynch, CLK). Cams take video and FPGA sucks the data out and write to a 256Mbyte RAM. CAMs are taking images simultaneously but they are not synchronized. The data may come at the same time or some time apart. FPGA writes each cam's data in a different place in RAM. Once the video taking is finished, it sends the data via SPI to CPU. That's pretty much it.
I am trying to see what would be the estimated LEs for something like this. I am choosing the Cyclone IV E series with 6K LEs. Is 6K LE enough? In this 6K, I would have to implement SPI, SDRAM and 2 camera interfaces and a few registers for CPU to coordinate operation.
