LOC constraint for signals of internal modules (Xilinx)

[spman]

Hi

How can I define LOC constraint for signals or registers of internal modules? Actually I don't want to do cumbersome works like routing an internal signal up to the top module and assign it to ports to see its value on LEDs only for debugging.

Thanks in advance.

 

[aruipksni]

Hi

How can I define LOC constraint for signals or registers of internal modules? Actually I don't want to do cumbersome works like routing an internal signal up to the top module and assign it to ports to see its value on LEDs only for debugging.

Thanks in advance.

read :

http://forums.xilinx.com/t5/Synthesis/How-to-avoid-signal-optimizing-in-synthesis/td-p/76056

 

[spman]

read :

http://forums.xilinx.com/t5/Synthesis/How-to-avoid-signal-optimizing-in-synthesis/td-p/76056

I'm not using ChipScope. I just want to force the pllacer to place a register or wire on a IO block.

 

[aruipksni]

I'm not using ChipScope. I just want to force the pllacer to place a register or wire on a IO block.

just look at the xilinx constrain guide :

**broken link removed**


have a look at IOB Constraint Examples section.

 

[mrflibble]

Yup, RTFM.

Also, you cannot place a constraint of a wire. You can constrain a register (flip-flop). Well, actually you can place a constraint on a wire, but that doesn't do anything. That's also in the fine manual somewhere.

 

[TrickyDicky]

If all you're doing is trying to connect an internal signal to an LED, why not route it out via the RTL. I dont think you could do this with LOCs anyway.