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List all possible ways to minimize the power dissipation of an ASIC chip

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macgradywk

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List all possible ways to minimize the power dissipation of an ASIC chip

Thx
 

kingslayer

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Hi there,

well it's quite general question, since there exist different ways to do it according to the power you are targeting (i.e., dynamic or static). And this is much more true for scaled technologies. Also, you should consider desing-time choices and run-time adaptation.

A good starting point, however, to reduce dynamic power is to use clock-gating: you stop/gate (i.e., you basically AND the clock with a control signal) the switching activity of unused regions of the chip. This brings dynamic power to zero (according to classical power dissipation analytics), but it's not a guarantee for static power. For instance, you might want to reduce it with power gating (i.e., cut-off supply voltage through sleep transistors).
Some microarchitecture choices then might be considered as power-optimization techniques, but they highly depend on the running applications: for instance a very accurate branch prediction can help you in reducing the power dissipation of an out-of-order processor.

If you are interested in the (pretty vast topic) you can start from classical references such as the "Low power methodology manual" written by Synopsys and ARM guys. It conveys a lot of the power dissipation problem.

Cheers
 

saurabhr8here

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A system-level solution would be to implement dynamic voltage and frequency scaling, which would require the designer to characterize the ASIC across a supply voltage and frequency range.

Foundries supply mult-Vt devices, based on your power/performance target, choosing the the correct Vt devices for your design (one or more) is crucial to limit leakage power.

Most SoCs and mainly the processor are made using synthesis auto place-route tools. Hence, it is important to create and efficiently characterize your standard cell library so that the synthesis tool gets a large variety of cell options to choose from to reach the power/performance targes. If the synthesis tool does not find the right drive strength cell, it moves to the next available cell which might meet the timing criteria but probably be higher leakage/dynamic power. Hence a rich (lots of options of drive strength, multiVt, different kinds of gates etc.) standard cell library is crucial for low power design.
 

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