Limitation of ODD parity generator "circuit is attached

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kunal1514

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odd parity generator

Hi All,

This is ODD Parity Generator. Can any body tell me what's the limitation of this circuit.

Regards
 

parity generator circuit

Each level is serial connected. You can parallel connect them. In RTL code, maybe:
out = ( (d1 ^ d1) ^ (d1 ^ d3) ) ^ d4;
Then, the delay will just be 3 level. But the delay of your figure is 4 level.
 

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