Std. cell library
Embedded memory compilers (memory libraries)
Basic IO (general-purpose)
Speciality IOs
Any kind of IPs (PLL, PHYs,...)
All of them are used in both front-end and back-end flows. But, the different views of these libraries are used in the different flows.
Front-end flow:
timing/power/noise model (synopsys liberty library as an example)
incompete layout model or phantom view (LEF or Milkyway FRAM)
behavioral model (verilog or vhdl model - not the netlist)
datasheet (well, it is needed also
)
Back-end flow:
full layout (GDS or Milkyway CEL)
transistor-level netlist (CDL or spice netlist)
transistor-level netlist with extracted parasitics