Libraries in VLSI design

[bala9383]

* Name the libraries used in VLSI design flow

* classify the libraries that are used in front end and back end (asic) design flow

 

[oratie]

Std. cell library
Embedded memory compilers (memory libraries)
Basic IO (general-purpose)
Speciality IOs
Any kind of IPs (PLL, PHYs,...)

All of them are used in both front-end and back-end flows. But, the different views of these libraries are used in the different flows.

Front-end flow:
timing/power/noise model (synopsys liberty library as an example)
incompete layout model or phantom view (LEF or Milkyway FRAM)
behavioral model (verilog or vhdl model - not the netlist)
datasheet (well, it is needed also )

Back-end flow:
full layout (GDS or Milkyway CEL)
transistor-level netlist (CDL or spice netlist)
transistor-level netlist with extracted parasitics

 

[ravipandu46338@gmail.com]

Frontend
1.technology libraries
a.Target library(.db)
b.linklibrary(.db format)
2.symbol library
3.technology independent library
a.Gtech library(genric technology)
b.synthetic library
c.Designware library

 

[sharif.shiek]

Hi bala,
in front end stage
Logic Libraries.
Technology Libraries
Target Library (from where tool will directly pick the components)
Link Library (which is used to resolve the references in our design)
Symbol Library
Synthetic Library (like adders, multipliers, etc..)
GTECH Libraries (Which are Technology Independent Libraries).

Back end Design
Physical Libraries Which contain all the physical characteristics of standard cells, Macros, Pad cells.
Logic Libraries (Target + Link Libraries) which contain timing and functionality information of STD cells and macro cells

 

[amitk3553]

Hi bala,
in front end stage
Logic Libraries.
Technology Libraries
Target Library (from where tool will directly pick the components)
Link Library (which is used to resolve the references in our design)
Symbol Library
Synthetic Library (like adders, multipliers, etc..)
GTECH Libraries (Which are Technology Independent Libraries).

Back end Design
Physical Libraries Which contain all the physical characteristics of standard cells, Macros, Pad cells.
Logic Libraries (Target + Link Libraries) which contain timing and functionality information of STD cells and macro cells

In the definition of target libraries, What is the meaning of componets or Which componets??

Is link library is like as connection library between the target libray and our design(RTL file)???

 

[aria62]

let's make it easy:
In front end (for example:synopsys design vision) you need at least 2 technology files:
1. a .db file for link and target library.
2. a .sdb file for symbol library.

in back end (for example soc encounter) you need at least these files:
1. timing libraries(.lib files)
2.physical libraries of standard cells(.lef files)
3.timing constraint file(.sdc file created in design vision)
4.io assignment file(you can create yourself)

- - - Updated - - -

let's make it easy:
In front end (for example:synopsys design vision) you need at least 2 technology files:
1. a .db file for link and target library.
2. a .sdb file for symbol library.

in back end (for example soc encounter) you need at least these files:
1. timing libraries(.lib files)
2.physical libraries of standard cells(.lef files)
3.timing constraint file(.sdc file created in design vision)
4.io assignment file(you can create yourself)

 

[amitk3553]

let's make it easy:
In front end (for example:synopsys design vision) you need at least 2 technology files:
1. a .db file for link and target library.
2. a .sdb file for symbol library.

in back end (for example soc encounter) you need at least these files:
1. timing libraries(.lib files)
2.physical libraries of standard cells(.lef files)
3.timing constraint file(.sdc file created in design vision)
4.io assignment file(you can create yourself)

- - - Updated - - -

let's make it easy:
In front end (for example:synopsys design vision) you need at least 2 technology files:
1. a .db file for link and target library.
2. a .sdb file for symbol library.

in back end (for example soc encounter) you need at least these files:
1. timing libraries(.lib files)
2.physical libraries of standard cells(.lef files)
3.timing constraint file(.sdc file created in design vision)
4.io assignment file(you can create yourself)

k. Then it means there is no role of synthetic and Gtech libraries in front end?

If it is, Then where is the role of these libraries??

 

[amitk3553]

Std. cell library
Embedded memory compilers (memory libraries)
Basic IO (general-purpose)
Speciality IOs
Any kind of IPs (PLL, PHYs,...)

All of them are used in both front-end and back-end flows. But, the different views of these libraries are used in the different flows.

Front-end flow:
timing/power/noise model (synopsys liberty library as an example)
incompete layout model or phantom view (LEF or Milkyway FRAM)
behavioral model (verilog or vhdl model - not the netlist)
datasheet (well, it is needed also )

Back-end flow:
full layout (GDS or Milkyway CEL)
transistor-level netlist (CDL or spice netlist)
transistor-level netlist with extracted parasitics

Hello friend,

Could u please tell me the Role of Synthetic Library and technology independent libraries in brief and details, as u wish.



Thanks with regards
cam