Liberty-cell and RTL-design Unit

[ManishGoel]

Is it true, that logic(behaviour description other than power-info,delay) would always be present in RTL-design unit whereas liberty-cell would contain both logic(defined using "function" attribute) and timing information ?

And also is it true, that if logic-description is present in both RTL-design unit and libert-cell than it would be in same format i.e statetable(udp) , boolean-expression ?

 

[kumar_eee]

If you look at the liberty files, they will have the timing and power info. The function also described like the following.

function : "A2*A1";

Are you talking about the RTL code of the same cell?

Yes, The RTL code will have the logic where as .lib will have logic & timing info. This is true only for std cells. You can open the verilog file & .lib file and see whats there inside.