Lfsr. Can somebody help me understand this code?

[Ferfil]

---

Code Verilog - [expand]
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module LFSR(
  input clk,
  output reg [15:0] LFSR = 65535
);
 
always @(posedge clk)
begin
  LFSR[0] <= LFSR[0] ^ LFSR[13] ^ LFSR[14] ^ LFSR[15];
  LFSR[15:1] <= LFSR[14:0];
end
endmodule

---

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please also help me with the testbench. thanks

 

[permute]

This is an LFSR. Presumably, taps 0, 13, 14, 15 have been chosen to generate a maximal length sequence. The selection of taps is not arbitrary, though several options exist. For example, the LFSR using taps 14, 15 would be the more common choice. The code is a shift register that shifts in a new bit based on the xor of bits 0, 13, 14, 15. If this is a maximal length sequence, then the lfsr state will reach all non-zero values and then repeat. The all-zero state would transition to itself, and is thus not part of the sequence.

The testbench should create a sequence that repeats after 65535 cycles.

If the taps do not create a maximal length sequence, then it will repeat after fewer cycles and will depend on the initial state.