Level Shifter Problem Using With FPGA

[strahd_von_zarovich]

Hi, i am trying to use TXS0102DCUR level shifter for I2C bus with FPGA. The problem is that when i am waiting for input from slave , i see weird voltage levels. While i am sending data and clock from FPGA nothing is wrong. However, after sending data request and if slave's response is low, it isn't low, it is about at 0.7V. Is it because FPGA can't sink current and input impedance is high-Z so i see 700mV. High pull-down resistor ll probably solve this problem what do you think ? :thinker:

FPGA's voltage levels is 1.8V and other side of the level shifter is 3.3V and nothing is wrong with the other side everything works perfectly. Level shifter has its own pull-up resistors for both sides with 10k.

 

[FvM]

Sounds like you are driving FPGA SDA line not correctly as open drain.

You say the I2C slave is driving SDA low but only reaches 0.7 V. What's the voltage on both sides of the level translator in this situation? What's the high level?

 

[strahd_von_zarovich]

Sounds like you are driving FPGA SDA line not correctly as open drain.

You say the I2C slave is driving SDA low but only reaches 0.7 V. What's the voltage on both sides of the level translator in this situation? What's the high level?

On slave's side , voltage levels are normal, it changes between 0 and 3.3V however on the FPGA's side there are 3 voltage levels, 0, 0.7V and 1.8V. When i am sending data from FPGA, voltage levels are normal, however after sending data request and put FPGA data line into high-z, even if slave's side is 0v FPGA side is 0.7v and i couldnt figure out why.

 

[FvM]

Thanks for clarifying. This shouldn't happen according to datasheet specifications.

Presume you connect 1.8 V I2C to A and 3.3 V to B side, OE input high as required.