LEC problem on DC 2006.06 ?

[bravobravo]

cadence lec compile_ultra

LEC problem on DC 2006.06 ?

When using DC 2004.06 as our synthesis tools, we have no problem on LEC for RTL-GATE session.

But when using DC 2006.06, it report that they are not L.E (using the same simple script to synthesis RTL).

And RTL reference design is USB or 16 bits cpu.

Anyone have the problem or can anyone tell me how to solve this ??

 

[niuniu]

compile_ultra no_autoungroup

this is because dc uses many high level synthesis which makes LEC very difficult. one way is to let DC write out svf file and use formality. but we still found there is abort.

have you use compile_ultra? if so, try to use these options like
compile_ultra -no_autoungroup -no_boundary_optimization -no_seq_output_inversion -exact_map
you can noticed that DC has turn on many optimization as default.

if QoR has not much difference and you care about LEC, just use compile, most of the time, comformal LEC can pass with analyze datapath, but if the constraints is too tight, some datapath logic still failed to pass.

 

[rameshsuthapalli]

compile_ultra lec

Hi all,

inn the svf file DC will write the design changes that happned in synthesis like namming chnges for the net and for the design(uniqufing naming styles).
grouping and ungrouping styles.in the previous vershions of the D.C there r not that much complx algorithems involved in synthesis so LEC able to understand the D.C changes.so better to use the formality or change u r namming rules(net and for design) to the verilog.

BR,
ramesh

 

[kpk]

flatten compile_ultra

Hi
I also faced such a problem with diferent versions.
Try using the -seq_constant switch in the set flatten model command.
Let me know if it works.
N we used Cadence(Verplex) LEC...