LDPC encoder and decoder on FPGA

[nanswamy]

Hi Friends,

I need to implement LDPC encoder and decoder on FPGA for below specification .
Can any suggest a suitable algorithm please.

1. Throughput:

A. Up to 8Mbps for low end devices like Spartan6
B. Up to 37Mbps for high end devices like Virtex6

2. Code Rate: a. 1/4 to 9/10 (at least in 6 steps)

B. Programmable on block by block basis
c. Programmable code matrix

3. Block Size: a. 1Kb to 64Kb depending upon throughput and code parameters
B. Programmable on block by block basis

4. Iterations Automatic/User defined

5. Soft Input data width Parameterizable 3 to 8 bits (compile time)

6. BER performance BPSK AWGN)

10-6 for Block length of ~2Kb @ Eb/No of ~3 dB for rate ½ and ~5 dB for rate
0.8

Please provide or refer any papers.
Thanks in advance.
Nan

 

[anventor]

Hi Nan,
When you say programmable code matrix, you mean any arbitrary code or structured code? You want to plug this into some system (BER) or you want it as hardware accelerator to verify your own custom LDPC code?

Regards,
Anventor

Hi Friends,

I need to implement LDPC encoder and decoder on FPGA for below specification .
Can any suggest a suitable algorithm please.

1. Throughput:

A. Up to 8Mbps for low end devices like Spartan6
B. Up to 37Mbps for high end devices like Virtex6

2. Code Rate: a. 1/4 to 9/10 (at least in 6 steps)

B. Programmable on block by block basis
c. Programmable code matrix

3. Block Size: a. 1Kb to 64Kb depending upon throughput and code parameters
B. Programmable on block by block basis

4. Iterations Automatic/User defined

5. Soft Input data width Parameterizable 3 to 8 bits (compile time)

6. BER performance BPSK AWGN)

10-6 for Block length of ~2Kb @ Eb/No of ~3 dB for rate ½ and ~5 dB for rate
0.8

Please provide or refer any papers.
Thanks in advance.
Nan

 

[nanswamy]

Hi Friend.


Thanks a ton for the response....

Programmable code matrix, I was meant that programmable "H" matrix.
I want to make an hardware accelerator on a Xilinx FPGA .

I want make an HDL simulation and FPGA setup for BER analysis .

Thanks
Swamy

Hi Nan,
When you say programmable code matrix, you mean any arbitrary code or structured code? You want to plug this into some system (BER) or you want it as hardware accelerator to verify your own custom LDPC code?

Regards,
Anventor