LDO - transient accuracy

[massive_attack]

hola!

I'd like to ask you about transient response of LDO.

typically it looks like this



I'm considering time \[\delta\]t3 . It's related to Cout slewing by feedback resistors or another sink.
The thing that in my simple design which is simple two stage opamp + pmos device this time is not shorter when I use 10x smaller resistors.
In the test bench I use worst case situation loading from 0 to Imax and back to 0 (tr,tf =1ns) with ESR=0(which is not true normally).

GBW of the system is 500kHz, PM > 70deg

What can be the reason of such long time? Should i worry that ? The output is about 70mV higher than should be.

regards

 

[chaojixin]

what kind of compensation did you used? the slew rate could be related to the compensation network.

 

[massive_attack]

I use basic Cout + ESR compensation which is enough in this situation.

 

[erikl]

What can be the reason of such long time?

Such an LDO can only source current, but not sink it, hence this slow decay.
If you really need it faster, you'd have to add a small controlled sink transistor.

Should i worry that ?

Depends on the application. Ask your customers!

The output is about 70mV higher than should be.

If absolute accuracy is important, Vref trimming should be considered.

 

[saro_k_82]

70mV difference is due to limited load regulation / finite output impedance. With two stage LDO, you can only try to increase the dc loop gain to reduce it most often at the cost of the moving the cut-off point in the load regulation characteristic to low frequencies.

 

[massive_attack]

writting 70mV i meant overshoot, which SLOWLY (100us) relaxes to proper output voltage at 1mA. It's even worse when load falls to 1u.

Another serious thing which i met is startup after turning on enable pin. Output voltage rises almost to vin and settles after 150us. The problem is that during the startup, PMOS device sources 3A!
how to prevent it, what kind of ciurcuit should i use.
any working examples ?

regards

 

[erikl]

writting 70mV i meant overshoot, which SLOWLY (100us) relaxes to proper output voltage at 1mA. It's even worse when load falls to 1u.

Quite clear, s. my posting above!

Output voltage rises almost to vin and settles after 150us. The problem is that during the startup, PMOS device sources 3A!

I = C * δV/δt . You load 150µF to 3V ?

how to prevent it

Does it hurt? If so: lower output cap -- or a soft start mechanism.

 

[massive_attack]

No, I load 1uF to 3.3V