Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

LDO question about quiescent mode

Status
Not open for further replies.

iamxo

Full Member level 4
Joined
Mar 22, 2006
Messages
227
Helped
16
Reputation
32
Reaction score
4
Trophy points
1,298
Location
Southeast Asia
Activity points
2,495
LDO simple question?

when the LDO is in quiescent mode, that is to say no output current is loaded.

the pass device is in subthreshold region or saturation region?

thanks all.
 

safwatonline

Advanced Member level 4
Joined
Nov 19, 2005
Messages
1,347
Helped
219
Reputation
438
Reaction score
47
Trophy points
1,328
Location
EGYPT
Activity points
9,059
LDO simple question?

normally sub threshold
 

    iamxo

    Points: 2
    Helpful Answer Positive Rating

iamxo

Full Member level 4
Joined
Mar 22, 2006
Messages
227
Helped
16
Reputation
32
Reaction score
4
Trophy points
1,298
Location
Southeast Asia
Activity points
2,495
Re: LDO simple question?

Thank you!

Added after 34 minutes:

safwatonline said:
normally sub threshold

normally?

Then, do you mean it will enter other regions in some condition?
 

hung_wai_ming@hotmail.com

Full Member level 6
Joined
Jan 5, 2004
Messages
383
Helped
52
Reputation
104
Reaction score
11
Trophy points
1,298
Activity points
2,464
LDO simple question?

When under full load, e.g. 100mA, PMOS should be on harder by decreasing the gate node voltage of PMOS output (assume it is PMOS output), then VSG is larger, and VSG-VTP > 0, and VSD always should be larger than VSDsat, so it is under saturation
When under 0 load, gate node of PMOS drives nothing and so it is trying to turn on or turn on slightly, so it can be regarded as "cut-off" region or sub-threshold region, as why sub-threshold because there is still a small amount of current flowing from PMOS to the resistive divider, so gate node is not exactly at VDD, but VDD minus some little voltages
 

    iamxo

    Points: 2
    Helpful Answer Positive Rating

iamxo

Full Member level 4
Joined
Mar 22, 2006
Messages
227
Helped
16
Reputation
32
Reaction score
4
Trophy points
1,298
Location
Southeast Asia
Activity points
2,495
Re: LDO simple question?

hung_wai_ming(at)hotmail.com said:
When under full load, e.g. 100mA, PMOS should be on harder by decreasing the gate node voltage of PMOS output (assume it is PMOS output), then VSG is larger, and VSG-VTP > 0, and VSD always should be larger than VSDsat, so it is under saturation
When under 0 load, gate node of PMOS drives nothing and so it is trying to turn on or turn on slightly, so it can be regarded as "cut-off" region or sub-threshold region, as why sub-threshold because there is still a small amount of current flowing from PMOS to the resistive divider, so gate node is not exactly at VDD, but VDD minus some little voltages

O, I see, thank you very much for your reply.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top