Shilpa poddar
Newbie
How miller cap affect the ldo psrr? Can anybody explain me this.
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Thanks for good explaination.I have one more doubt. which frequency range this effect will be visible? According to my knowledge at low frequency loop gain of ldo decide pssr as we go to high frequency loop gain deteriorate and output capacitor decide the pssr.The most common Miller comp scheme puts the
cap across the pass FET D, G terminals against a
weak transconductance amplifier.
Consider that there is an external capacitor that
is significantly larger in value. That makes VOUT
for purposes of discussion, DC-constant.
Now if you perturb VIN upward, you will increase
the voltage across the compensation capacitor
(attached to D = VOUT) as its gate is in-the-moment
positioned relative to VIN (=S) by the gate overdrive
required to make IOUT. The increased comp cap
voltage must pull on pass FET G, downward. That
increases pass FET current at the same time VIN
is rising, so obviously degrades PSRR; the pass FET
has significant gain when not in "dropout" (linear
region) and a bit remaining even in dropout.