LDO output volatge peak during turn of the load

[vovan76]

Hi
When LDO Vout go lower LDO current is go higher and Voltage is up but Voutgo up LDO feedback close the pass gate but how this volateg is going to discharge.
there is no discharge current When Iload is very low or = 0 and LDO resitor feedback divider in genral has very low current.
This scenario can accure when all LDO load turrn off and due to LOW BW LDO Vout jump up .
Does anybody deal with this issue and how can I solve this Vout peak.

 

[goldsmith]

Hello Dear Vovan
What do you mean by :"but how this volateg is going to discharge." ?
Best Wishes
Goldsmith

 

[barry]

What is it you need to discharge?

 

[vovan76]

When Vout is going over the desired voltage Vnom the feedback should return this over voltage to Vnom in other word descharge the LDO output capacitor.
In order to discharge capacitor should be the Current to ground but in case Iload=0 how this capacitor going to discharge?

 

[goldsmith]

is your mean out put capacitor ? what kind of LDO arrangement , do you talking about that ?

 

[vovan76]

hi
Let's agree that LDO its a circuit with feedback
output LDO cpacitor connected to LDO ouput.
If some circuit has a feedback and goal of the feedback is keep ouput voltage stable and this voltage is changed due to LDO load so feedback will try to return the Vout to nominal Value i.e. discharge the capacitnace on this ouput.

 

[goldsmith]

I know that what is an LDO , if you want that i help you at greatest way , you should attach your circuit here . The LDO regulators have many families .

 

[vovan76]

I'm talking about regular LDO with amplifer and PMOS or NMOS path gate and resistor feedback divider not something especial

 

[goldsmith]

Ok , no problem . if the out put become lower than your desired , value , the feed back network will sense it , quickly , and then the out put voltage of the op amp will increase and thus the ib of first transistor will increase and thus the out put voltage will increase . and the same behavior for increasing the voltage ( suddenly change ). and the value of the out put capacitor will not be very high , it will be about some micro farad .
Good luck
Goldsmith

 

[barry]

Okay, so you've got an LDO with an output cap and a load. The cap is charged to Vout and suddenly the load is removed. The feedback will try to drive the pass-element off, and current will flow through the cap. The response time of the loop will determine how long it will take to drive the pass-element off, and, thus, the amount of overshoot.

Think of it this way: if you have an infinitely fast loop, you'll have zero overshoot; if you have a very slow loop, the output will rise to the value of the input voltage(a very bad regulator).

 

[checkmate]

You are right. There is no discharge path so Vout always remains elevated.
Many ways to tackle this, including a minimum load (ie current sink), or if there's discharge through the feedback tree.
Otherwise, a larger output cap will reduce the magnitude of the overshoot.

Besides, this "overshoot" should already be taken into account in the design phase based on the line regulation spec.
If the loop response is not fast enough to regulate the output voltage within spec upon a step response from max current to zero (or vice versa), then the spec has not been met in the first place.

 

[barry]

Checkmate is absolutely right about designing this properly. That's why there are so many different types of regulators: fast-response, low-noise, etc. Also, some regulators actually require a minimum load.

 

[dick_freebird]

Some LDOs optimized for very light load, have added a NMOS
sink to the output (sort of Class AB). A high-side-only regulator
is entirely helpless against load-dump-to-zero. Of course the
feedback network usually sets some sort of minimum
conductance.