LDO open loop gain doubt

[sneha rayala]

Hi ,

below is the schematic and plot of openloop gain and phase of LDO .
PMOS folded cascode opamp is used as error amplifier , pmos folded cascode gain and phase plots are in BW image 72db gain .
my question here is that in LDO open loop gain plot I see gain dropping from beginning . why is this happening , is it because the pole of error amplifier pushed further towards origin ? if that is the case so for one pole I should see 20db drop in gain per decade but I am seeing lot more than that . I Have also attached stability summary of LDO

 

[dick_freebird]

The output stage is a big Miller pole that varies hugely
with load impedance / current and pass FET headroom.
Tough to stabilize and especially if you think you're
going to get a free "comp cap" from the pass FET
Cdg rather than an explicit one that's isolated from
the load effect. PMOS pass FET also tends to hurt
HF PSRR a lot especially if driven by a weak op
(error) amp.

 

[Dominik Przyborowski]

Maybe show us a bode plots with logarythmic frequency scale?