LDO- accuracy, stability, consumption

[massive_attack]

Hello,

As it's known , to have good load regulation and low deflection voltage high open loop gain is needed.
When the spec needs ultra low ground current <10uA and good accuracy and fast response gain+buffer are needed.

I wonder about using single stage opamp with unity gain buffer, but to achieve PM>60deg i need to lower amplifier's gain. Low current amplifier => smal transistors area => more offset => lower accuracy
Low gain influences load regulation.

What kind of amplifer do you use with unity gain buffer ? or what kind of buffer can i use. i tried source follower but the result is almost the same.

kind regards

 

[erikl]

... or what kind of buffer can i use.

Just provide enough current (I = C * δV/δt) to the output stage!

 

[massive_attack]

Just provide enough current (I = C * δV/δt) to the output stage!

well, the thing is the current is the constraint.

 

[erikl]

well, the thing is the current is the constraint.

Dynamic current capability is meant; static (quiescent) current may be much lower. A no-load quiescent current of ≦10µA should be possible for a max. LDO output current up to ≈10mA.

 

[massive_attack]

i've used slew rate enhancement technique in the buffer stage, but the static current in output branch (5uA) is not enough tu push forward the pole.
I had to lower amplifier's gain using transistors with small areas. Finally was able to stabilize the circuit at all loads, but got bigger output voltage error because of lower gain(open loop gain 40dB).
Maximum load current is 150mA and pass device is 20m/0.4u

 

[dick_freebird]

You can consider a couple things.

One, if you make a more complex error amplifier with some
extra diff pairs, and operate these with asymmetric sizing,
you can detect large input error and use that to engage
an "overdrive" bias that helps with slew rate yet costs no
great quiescent current. It needs to be safely disengaged
across the DC load range, of course. You push bias up
when the loop is not closed, and this does not impact
closed loop stability if you manage the transition well.

You can also consider a dual loop, where you have a fast
low-gain amplifier that is responsible for the dynamic current
demand and HF stability, with limited voltage authority, and
a very slow amplifier that has the high DC gain and pushes
the fast amp to center.

 

[alvays]

HI, dick_freebird

Your thread is helpful for me. But can you show me any further clue or some related papers for these two papers? I didn't find them.

You can consider a couple things.

One, if you make a more complex error amplifier with some
extra diff pairs, and operate these with asymmetric sizing,
you can detect large input error and use that to engage
an "overdrive" bias that helps with slew rate yet costs no
great quiescent current. It needs to be safely disengaged
across the DC load range, of course. You push bias up
when the loop is not closed, and this does not impact
closed loop stability if you manage the transition well.

You can also consider a dual loop, where you have a fast
low-gain amplifier that is responsible for the dynamic current
demand and HF stability, with limited voltage authority, and
a very slow amplifier that has the high DC gain and pushes
the fast amp to center.

 

[erikl]

If you need higher gain, you could also use a load (i.e. out current) dependent frequency compensation.

... some related papers ...

**broken link removed** (free download)
A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation
A frequency compensation scheme for LDO voltage regulators
Pole-zero tracking frequency compensation for low dropout regulator
A Low-dropout Regulator with Unconditional Stability and Low Quiescent Current
A Low-Voltage, Low Quiescent Current, Low Drop-Out Regulator (free download)