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LCD Driver- OM4068 and PIC

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Dec 4, 2010
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I am doing what I thought would be very simple--unidirectional data transfer from my microcontroller to the OM4068 (**broken link removed**). The OM4068 has a data, clk, and enable line, and according to the datasheet, appears to not require any sort of indication from the device sending data (the microcontroller) that the MCU is about to start sending data, or that it is has stopped sending data. From what I understand of the OM4068, I just needed to put the raw bits at its doorstep, and it will handle the rest.

I am following the rules set out in the datasheet (verified on my logic analyzer): I pull the enable line high for the duration of communication (this enables the register holding incoming data to shift its information to the second register), and I make sure the DAT line is high well before and after the CLK line pulses. My CLK is at ~13kHz, but is not continuous--it is part of a routine called at the end of each iteration of a function, and CLK cycles 32 times each iteration of the function, to fill up the 32bit register with corresponding DAT pulses.

Sorry for the long explanation, but what I see on every output pin of the OM4068 is just a square wave at a frequency of ~66Hz, which the datasheet says is the refresh rate of the LCD screen. High and low levels of the square wave are 0V and ~VLCD. It doesn't look as though the OM4068 is pulling any of its output pins LOW that correspond to the 0's arriving at the DAT line, nor does it look like its pulling any pins HIGH that correspond to 1's arriving at the DAT line. It just looks like it's not doing much at all. I am pulling M0 high (1) and M1 low (0) to indicate I am in static drive mode (as per datasheet).

Does it sound like I'm missing something, like a SETUP routine to tell the OM4068 that what is coming next at the DAT line should be treated as data to put in the register, and not just noise? Should I be running this clock continuously, and not in 32-pulse bursts at the end of my main routine?

I'd appreciate any help, thank you. Even if anybody were to look at the datasheet and tell me if I'm missing something obvious. I've verified signal levels meet threshold requirements using custom set triggers on the logic analyzer.


No experience of that chip, but just reading the datasheet it infers that once the SCLK pulse is stopped it goes into standby and all outputs are Tri-stated.

Perhaps if you set up a test routine so it is outputting a 32 bit string of data in a continuous loop you might see things better.
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