Layout techniques (Rg reduction)

IvanTheTerrible · Mar 13, 2011

The layout on the right reduces Rg by a factor of 4 by having 2 Rg/2 in parallel, how does the layout on the left reduces Rg?

Milad-D · Mar 13, 2011

I think the left one also reduces the rg by 4. For RF transistors, both ideas are used to reduce the rg.

vijaymishra · Mar 14, 2011

Intutively, the layout technique on the left, is like, applying same potential to either ends of a resistor, thereby making them in parallel.

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