Feb 17, 2006 #1 G gevy Full Member level 6 Joined Nov 17, 2004 Messages 340 Helped 60 Reputation 120 Reaction score 29 Trophy points 1,308 Location Russia Activity points 2,167 1. What is layout rules to design power switching NMOS and PMOS transistors on chip, if its currents are more than one ampere? 2. What is noise isolation methods of control circuit from power transistors?
1. What is layout rules to design power switching NMOS and PMOS transistors on chip, if its currents are more than one ampere? 2. What is noise isolation methods of control circuit from power transistors?
Feb 20, 2006 #2 L layout_designer Member level 5 Joined Jan 9, 2006 Messages 87 Helped 14 Reputation 28 Reaction score 6 Trophy points 1,288 Activity points 1,869 Hi Refer alan hastings. A clear understanding can be had. NMOS especially has more considerations. 1. One isolation technique is to place the powerMos far away from core. 2. Deep trenches are used regards
Hi Refer alan hastings. A clear understanding can be had. NMOS especially has more considerations. 1. One isolation technique is to place the powerMos far away from core. 2. Deep trenches are used regards
Feb 22, 2006 #3 O omsi Member level 5 Joined Jan 24, 2006 Messages 93 Helped 7 Reputation 14 Reaction score 7 Trophy points 1,288 Location London Activity points 2,105 gevy said: 1. What is layout rules to design power switching NMOS and PMOS transistors on chip, if its currents are more than one ampere? 2. What is noise isolation methods of control circuit from power transistors? Click to expand... use double gaurd rings.
gevy said: 1. What is layout rules to design power switching NMOS and PMOS transistors on chip, if its currents are more than one ampere? 2. What is noise isolation methods of control circuit from power transistors? Click to expand... use double gaurd rings.
Feb 23, 2006 #4 S sambireddy Junior Member level 1 Joined Feb 3, 2006 Messages 16 Helped 1 Reputation 2 Reaction score 0 Trophy points 1,281 Location Bangalore Activity points 1,447 usage of deep nwell i.e sorround the transistors with the deepnwell as a ring. this can be the best way to reduce the substrate noise caused by the high power transistors.
usage of deep nwell i.e sorround the transistors with the deepnwell as a ring. this can be the best way to reduce the substrate noise caused by the high power transistors.
Feb 23, 2006 #5 P pratyusha Junior Member level 1 Joined Jan 12, 2006 Messages 16 Helped 1 Reputation 2 Reaction score 1 Trophy points 1,283 Activity points 1,452 specially designed mos for handling high currents like "DMOS" are supported by some processes . we can use this special devices if available
specially designed mos for handling high currents like "DMOS" are supported by some processes . we can use this special devices if available