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Layout of power switching NMOS and PMOS

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gevy

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1. What is layout rules to design power switching NMOS and PMOS transistors on chip, if its currents are more than one ampere?

2. What is noise isolation methods of control circuit from power transistors?
 

layout_designer

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Hi

Refer alan hastings. A clear understanding can be had.
NMOS especially has more considerations.

1. One isolation technique is to place the powerMos far away from core.
2. Deep trenches are used

regards
 

omsi

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gevy said:
1. What is layout rules to design power switching NMOS and PMOS transistors on chip, if its currents are more than one ampere?

2. What is noise isolation methods of control circuit from power transistors?

use double gaurd rings.
 

sambireddy

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usage of deep nwell i.e sorround the transistors with the deepnwell as a ring. this can be the best way to reduce the substrate noise caused by the high power transistors.
 

pratyusha

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specially designed mos for handling high currents like "DMOS" are supported by some processes . we can use this special devices if available
 

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