I have some digital schematic( not verilog/VHDL), and I want to generate the layout automatically. The wires of each devices should be connected well when the layout is generated.
Many tools have schematic driven layout but in the
cases I've been exposed to, this is really more of a
"schematic driven stupid placement plus a tangled
up mess of flight-lines".
The schematic source may or may not be what your
layout tool (=?) can do anything with. And translation
between tools is kind of a tar pit.
I have some digital schematic( not verilog/VHDL), and I want to generate the layout automatically. The wires of each devices should be connected well when the layout is generated.
If you have the schematic captured, then you have a netlist! And it's READY for (digital) physical design! Using virtuoso or some combination of custom layout tool would be ridiculously naive.