Hi all,
I'm looking for a way to identify my generated bitstream design from the file. I've found **broken link removed** paper. They talk about a comment string in the bitstream. Does anyone know a way to add this comment in the bitstream ?
If I remember correctly, the CRC is at the end of the file.
Make the changes you require and recalculate the CRC of the file.
Also, if you have the design programmed on an FPGA - then you can use the Verify command of the JTAG programming tool to find out if the file on the PC and the one on the FPGA are the same.
I'm pretty sure that any ASCII header data (i.e. comments) are not part of the bitstream and there shouldn't be any effect on the CRC of the bitstream if it's changed. Though I couldn't verify that on Lattice's website but I did find https://www.latticesemi.com/en/Support/AnswerDatabase/2/3/2/2329.aspx, where they suggest stripping the ASCII header.
The simplest check is add/change/remove a character from in the current header and see if the FPGA still loads.