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Latches in Altera designs?

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alexz

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Latches in alera CPLDs

The following is a quote from the Altera's Recommended HDL
Coding Styles paragraph 6:

"Altera recommends that you design without the use of latches
whenever possible."

What does it mean?
 

jcchan

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Latches in alera CPLDs

altera timing engine can not analyze it.
 

alexz

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Re: Latches in alera CPLDs

But I can still use it in the design can't I?
 

Hero

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Re: Latches in alera CPLDs

Hi,

You can implement laches using asynchronous feedback paths in your cobinational logic. Probably you will have problems with time simulations.

Also you need to consider possible metastablilty problems. So don't use latch and inverted latch output at same time.
Setup and hold times are very routing dependant and upredictable.

With synchronuos solutions you can easy predict all timing parameters in your design.
 

alexz

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Re: Latches in alera CPLDs

What are the disadvantages of doing the following latch?

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

entity latching is
port
(
signalIn : in std_logic_vector(15 downto 0);
signalOut : out std_logic_vector(15 downto 0);
inEn : in std_logic
);
end latching;

architecture latch_behaviour of latching is

begin
signalOut <= signalIn when inEn = '1' ;
end latch_behaviour ;
 

Iouri

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Latches in alera CPLDs

Alexz,

It means you are not allowed to implimet something like RS flip-flop, and async design, all of your storage, needs to sync with input clock.
It is not only Altera, it is mostly all FPGA vendors...

Good luck!!!!
 

Hero

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Re: Latches in alera CPLDs

Hi,

Most macro cell architectures only support flip-flops not latches. Without this support you need to implement latches with combinational logic using feeback paths. In this case your design is very timing and routing dependant and inefficient.

So if you really don't need latches use registers. If you use programmable logic array technology you can use leatches and registers without restrictions
 

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