latch up - which device induces latch-up?

[skysky]

latchup

discription:

the simulation result of current of the IC is less than 10uA,
but the test result is more than 170mA.
When measuring , the current of the IC first rise to 10mA slowly, then reach 170mA quickly.

So, I think that latch-up happens somewhere. The question is that which device induce latch-up?

The doubtful schematic is shown in the figure.

 

[semiartist]

latchup iv curve

usuasly, the latch up is due to layout, the figure u posted, i think, the p+(bulk of nmos) should be placed close to nwell, that's to say, it should be placed at the right side of nmos.

 

[erikl]

Re: Help: latch up

skysky,
just an idea, resp. questions:
<D04> are in a separate n-well (separate from <D59> and pmos P18 n-well)?
What's the distance between these two n-wells? GuardRing in-between?

When "on", the circuit can draw a rather high current (≈100mA), right?
What's the distance between the nmos M1 and the closest n-well?

 

[skysky]

Re: Help: latch up

Thank everybody for your attention!

<D04> are in a separate n-well (separate from <D59> and pmos P18 n-well).
The distance between these two n-wells is about 17um without GuardRing. The width of mos is 0.6um.

When "on", the circuit draws a rather high current about 170mA.

The distance between the nmos M1 and the closest n-well is largerer than 100um.

what happened in the circuit? Which device caused latch-up ?
Thanks!

 

[stefannm]

Re: Help: latch up

When you say the current increases slowly, do you mean in time or in response to changing supply voltage?

Can you observe or control your output A_B during this situation. It would be interesting to know its potential. You may be able to narrow down the search that way.

Can you control your gate voltages of the mosfets in all 4 possible configurations? What are the respective supply currents and what is the output potential?

configurations
pmos off, nmos off
pmos on, nmos off
pmos off, nmos on
pmos on, nmos on

Thanks,

Also, layout or floor plan could be helpful.

 

[erikl]

Re: Help: latch up

<D04> are in a separate n-well (separate from <D59> and pmos P18 n-well).
The distance between these two n-wells is about 17um without GuardRing.
The width of mos is 0.6um. ???

When "on", the circuit draws a rather high current about 170mA.

The distance between the nmos M1 and the closest n-well is largerer than 100um.

I think the distances are big enough, even for non-epi substrate (and probably larger than the DRs would require). I don't understand the mos width info above, because your schematic tells (at least) w=1.8mm for the PMOS (if I read it correctly), which is reasonable - however not essential for your problem here.

The slow current rise IMHO doesn't really indicate a latch-up. The high current value of 170mA could indicate that one of the resistor banks (possibly together with its adjacent diodes' bank and the MOS switch) is short-circuited.

In your cross-section drawing I see a FOX distance between the MOS source and bulk terminals, i.e. they are not really adjacent. Could it be possible, that the voltage drop over the n-well resistance between the source and bulk contacts triggers the parasitic vertical pnp BJT (source (or drain) = emitter, n-well = basis, psub = collector), so that the rest of the circuit <D04, R1:R5, M1> is short-circuited?

If you can realize the control sequences suggested by stefannm (above), you might perhaps find out about this possibility.

Good luck! erikl

 

[Teddy]

Help: latch up

I am just a dummy here but there is a thing I don't like on your circuit.
In my opinion if you use the structure you show as a output structure and it will be turning on/off the PMOS/NMOS then the diodes will not have defined voltage on the negative terminal.
That I think could be simulated IF you have correct model. Mostly diode is "just a diode" so the models suck.

So the be more precise: what will happen if PMOS is ON and NMOS off.
The A_B node will be pulled "Hi" and the diodes will D<5:9> will have defined Plus/mius potential - IF you have resistive load! If you put capacitive load there what those diodes will do??? Also - the bulk of PMOS is tied to the diode NWELL - which in my opinion is not defined so you have another NWELL which is undefined.
As for diodes D<0:4> - what defines the NWELL potential? It will be dragged up to A_B potential.

If you consider this - you might have some leakage through the diodes or the latchup as you said - but latchup you should be able to rule out by testing for it by forcing current to A_B node.

I just don't think this is a "safe" structure.

 

[skysky]

Re: Help: latch up

I think the distances are big enough, even for non-epi substrate (and probably larger than the DRs would require). I don't understand the mos width info above, because your schematic tells (at least) w=1.8mm for the PMOS (if I read it correctly), which is reasonable - however not essential for your problem here.

The slow current rise IMHO doesn't really indicate a latch-up. The high current value of 170mA could indicate that one of the resistor banks (possibly together with its adjacent diodes' bank and the MOS switch) is short-circuited.

In your cross-section drawing I see a FOX distance between the MOS source and bulk terminals, i.e. they are not really adjacent. Could it be possible, that the voltage drop over the n-well resistance between the source and bulk contacts triggers the parasitic vertical pnp BJT (source (or drain) = emitter, n-well = basis, psub = collector), so that the rest of the circuit <D04, R1:R5, M1> is short-circuited?

If you can realize the control sequences suggested by stefannm (above), you might perhaps find out about this possibility.

Good luck! erikl

Sorry, there is mistake in my words. The length of mos gates is 0.6um.

The diode DP has a parasitic pnp, whose collector is the substrate.
Then, there is a current path formed by <R5:R9> and the parasitic pnp.
I think the parasitic pnp induce large source current.
So, I think, it is a parasitic pnp, not a latch-up, which ruined the circuit.

 

[dick_freebird]

Re: Help: latch up

If it is latchup then you will see a hysteretic I-V curve with a holding
voltage lower than trigger voltage. But punchthrough / reachthrough
will not show much hysteresis. Look at the curve and decide which is
more the case.

Some design kits fail to model the parasitic devices of things like
diodes, assuming application rules prevent these from activating.
That makes you responsible for the "fine print".

 

[Krishh]

Re: Help: latch up

Latch-up prevention in MOS IC_°Ù¶ÈÎÄ¿â go through this data.. It contains many useful simulation results for latch up

 

[dick_freebird]

You're looking in the wrong place for clues, a liquid crystal or
thermal image on a live part would narrow it right down.

 

[starsunmoon]

liquid crystal probably is faster and the cheapest that you can try it yourself, before you try thermal imaging.

also check the layout with foundry's latchup document if any.