Dear all,
I am drawing layout using 0.18um cmos. In my design, there are some building blocks' output/input pin connected with analog ESD pad. After I do the DRC checking, it said that there is latch up problem and suggests me to add guard ring of this block. This block already highly packed (upper part is pmos and lower part is nmos). I just could add p+ and n- guard ring with whole building block instead of upper part pmos surrounded by n-guard ring and lower part nmos surrounded by p-guard ring. However, the same error is appeared. How could I fix it? I could not use digital ESD pad because of some reason.
thanks
wccheng