Latch up problem in layout.

[wccheng]

Dear all,

I am drawing layout using 0.18um cmos. In my design, there are some building blocks' output/input pin connected with analog ESD pad. After I do the DRC checking, it said that there is latch up problem and suggests me to add guard ring of this block. This block already highly packed (upper part is pmos and lower part is nmos). I just could add p+ and n- guard ring with whole building block instead of upper part pmos surrounded by n-guard ring and lower part nmos surrounded by p-guard ring. However, the same error is appeared. How could I fix it? I could not use digital ESD pad because of some reason.

thanks

wccheng

 

[gafsos]

Adding 2 (or 3 row if possible) contacts in PTAP/ surrounding urs blocks

 

[ESDSolutions]

Hi

Sometimes the guard ring is not enough and a certain distance between the NMOS and PMOS is needed. The N+ source connected to gnd and the PMOS P+ source connected to Vdd must be separated by a certain minimun distance. I do not have access to the DRC rules at this time. I am sure that such is mentioned in the DRC guidelines from the foundry.

 

[k_90]

yea EDSsolutions is correct.

You need a minimum distance from the esd device to and unrealated circuit. There is a minimum distance, normally the distance between the esd nmos device to the nearest pmos device with and without a guard ring. The guard ring decreases the minimum by about halve. Watch out we have seen esd rules ignoring resistors making it look as if everything was conected to power, just one to watch.

The design rules will tell you the minimum distance.