[SOLVED] Latch created in FSM

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module main(a,b,c,d,e,R,en,clk,S,z,k,count,reset);
  input [3:0]a;
  input [3:0]b;
  input [3:0]c;
  input [3:0]d;
  input [3:0]e;
  wire [3:0]x;
  wire [3:0]y;
  input reset;
 output wire [3:0]z;
 output reg [3:0]k;
 output reg [3:0]R;
 output reg [2:0]S=3'b000;
reg [2:0]next_S=3'b000;
  input en;
  input clk;
 output reg count;
 
 
parameter S0=3'b000;
parameter S1=3'b101;
parameter S2=3'b110;
parameter S3=3'b111;
  
  //code for addition
  assign z = x+y;
  // code for 4:1 Mux containing b,c,d & e
  assign x = ( S[1:0] == 0 )? b : ( S[1:0] == 1 )? c : ( S[1:0] == 2 )? d : e;
  //code for 2:1 Mux for a & Register
  assign y = ( S[2] == 0 )? a : R;        //Register selected when select line is 1
  
  //control path
  //z_reg_out
  always@(posedge clk)
  begin
    if(en)
      R<=z;
    else R<=R;
  end
  
  always@(posedge clk)
  begin
  if(reset)
  k<=0;
else
  k<=R;  
  end  
  
  always@(posedge clk)
  begin
  if(reset)
  S<=3'b000;
else
  S<=next_S; 
  end  
  
  //next_state_logic & control_output_generation 
   always@(*)
  begin
    case(S)
      
      S0:if(en)
            next_S=3'b101;
          else next_S=S;
            
      S1:if(en)
            next_S<=3'b110;
          else next_S<=S;
            
      S2:if(en)
            next_S<=3'b111;
          else next_S<=S;
            
      S3:if(en)
      begin     
            next_S<=3'b000;
          end
          else next_S<=S;
            
      default:begin
      R<=R;
end
 
    endcase
  end