Shubham_Pandia
Newbie level 1
Why is a latch being created in the following code?
The latch is created in next_S under next state logic
I am new to verilog and slightly confused in this respect.
The latch is created in next_S under next state logic
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 module main(a,b,c,d,e,R,en,clk,S,z,k,count,reset); input [3:0]a; input [3:0]b; input [3:0]c; input [3:0]d; input [3:0]e; wire [3:0]x; wire [3:0]y; input reset; output wire [3:0]z; output reg [3:0]k; output reg [3:0]R; output reg [2:0]S=3'b000; reg [2:0]next_S=3'b000; input en; input clk; output reg count; parameter S0=3'b000; parameter S1=3'b101; parameter S2=3'b110; parameter S3=3'b111; //code for addition assign z = x+y; // code for 4:1 Mux containing b,c,d & e assign x = ( S[1:0] == 0 )? b : ( S[1:0] == 1 )? c : ( S[1:0] == 2 )? d : e; //code for 2:1 Mux for a & Register assign y = ( S[2] == 0 )? a : R; //Register selected when select line is 1 //control path //z_reg_out always@(posedge clk) begin if(en) R<=z; else R<=R; end always@(posedge clk) begin if(reset) k<=0; else k<=R; end always@(posedge clk) begin if(reset) S<=3'b000; else S<=next_S; end //next_state_logic & control_output_generation always@(*) begin case(S) S0:if(en) next_S=3'b101; else next_S=S; S1:if(en) next_S<=3'b110; else next_S<=S; S2:if(en) next_S<=3'b111; else next_S<=S; S3:if(en) begin next_S<=3'b000; end else next_S<=S; default:begin R<=R; end endcase end
I am new to verilog and slightly confused in this respect.
Last edited by a moderator: