kindly help in this vhdl testbench code

preet said:

slave_clkedge <= '1' when SLAVE_CPHA = SLAVE_CPOL
else '0';

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assign slave_clkedge = SLAVE_CPHA == SLAVE_CPOL ? 1'b1 : 1'b0;

preet said:

-- Define a 3-bit counter to count SCK edges and data into register so that parallel
-- register is loaded. Use same clock edge that is used to input data
SLAVE_IN_CNTR: process(sck, reset)
begin
-- Clear output register
if (reset = RESET_ACTIVE) then
slave_cnt_int <= (others => '0');

-- On SLAVE_CLKEDGE edge of clock count
elsif sck'event and sck = slave_clkedge then
if ss_n /= ALL_ONES then
slave_cnt_int <= slave_cnt_int + 1;
end if;
end if;

end process;

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generate
if ( SLAVE_CLKEDGE == 1) // use a rising edge clock
always @ (posedge sclk or posedge reset) begin
  if ( reset ) begin
    slave_cnt_in <= 3'b0;
  end else if (ss_n != ALL_ONES) begin
    slave_cnt_int <= slave_cnt_int + 3'b1;
  end
end
else // SLAVE_CLKEDGE == 0 // use a falling edge clock
always @ (negedge sclk or posedge reset) begin
  if ( reset ) begin
    slave_cnt_in <= 3'b0;
  end else if (ss_n != ALL_ONES) begin
    slave_cnt_int <= slave_cnt_int + 3'b1;
  end
end
endgenerate

ads-ee said:

Just realized I used end instead of endgenerate :shock: oops!

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preet said:

is it possible to use if outside always block....

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