kindly help in this vhdl testbench code

[preet]

I am trying to convert this vhdl testbench code to verilog testbench, kindly help me to convert this part of code

slave_clkedge <= '1' when SLAVE_CPHA = SLAVE_CPOL
else '0';

-- Define a 3-bit counter to count SCK edges and data into register so that parallel
-- register is loaded. Use same clock edge that is used to input data
SLAVE_IN_CNTR: process(sck, reset)
begin
-- Clear output register
if (reset = RESET_ACTIVE) then
slave_cnt_int <= (others => '0');

-- On SLAVE_CLKEDGE edge of clock count
elsif sck'event and sck = slave_clkedge then
if ss_n /= ALL_ONES then
slave_cnt_int <= slave_cnt_int + 1;
end if;
end if;

end process;


Regards

 

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slave_clkedge <= '1' when SLAVE_CPHA = SLAVE_CPOL
else '0';

assign slave_clkedge = SLAVE_CPHA == SLAVE_CPOL ? 1'b1 : 1'b0;

-- Define a 3-bit counter to count SCK edges and data into register so that parallel
-- register is loaded. Use same clock edge that is used to input data
SLAVE_IN_CNTR: process(sck, reset)
begin
-- Clear output register
if (reset = RESET_ACTIVE) then
slave_cnt_int <= (others => '0');

-- On SLAVE_CLKEDGE edge of clock count
elsif sck'event and sck = slave_clkedge then
if ss_n /= ALL_ONES then
slave_cnt_int <= slave_cnt_int + 1;
end if;
end if;

end process;

generate
if ( SLAVE_CLKEDGE == 1) // use a rising edge clock
always @ (posedge sclk or posedge reset) begin
  if ( reset ) begin
    slave_cnt_in <= 3'b0;
  end else if (ss_n != ALL_ONES) begin
    slave_cnt_int <= slave_cnt_int + 3'b1;
  end
end
else // SLAVE_CLKEDGE == 0 // use a falling edge clock
always @ (negedge sclk or posedge reset) begin
  if ( reset ) begin
    slave_cnt_in <= 3'b0;
  end else if (ss_n != ALL_ONES) begin
    slave_cnt_int <= slave_cnt_int + 3'b1;
  end
end
endgenerate

That should do the trick. Not sure if you wanted compile time selection of clock edge, but I added the generate to select either.

Regards

 

[preet]

Dear ADS-EE

is it possible to use if outside always block....

Regards

 

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it's in the generate, it's not a sequential statement in this case. I'm assuming that SLAVE_CLKEDGE is a constant that defines which clock edge the design should use. Just realized I used end instead of endgenerate :shock: oops!

 

[mrflibble]

Just realized I used end instead of endgenerate :shock: oops!

pre-caffeine coding?

is it possible to use if outside always block....

Sure, but it's not a very meaningful question. You can use an if statement inside an initial block, which is also 100% outside of any always block. And from this you conclude ... ?