Killer Input capacitance

[archiees]

hi,
I am designing a transimpedance amplifier which needs to amplify around 100pA of current to few mVs , the signal frequency is from 10Khz to 10 Mhz. I start with a 1M ohm resistor to convert this current into voltage and use a FET in a source follower configuration for pre-amplification.
My problem is the high impedance input signal source. I model it as a current source in parallel with a 20pF capacitance.
This 20 pF capacitance with the input resistor of 1Mohm forms a high frequency pole - severely limitting my BW to less than 50 KHz.
I don't want to reduce my 1M resistor which will reduce my Transimpedance gain. As my signal before being fed to the preamplifier should be higher than the signal noise floor.
So, i am stuck and i don't know how to keep the sufficient gain upto 10MHz. Please help.

 

[suria3]

1Mohm of resistor will definitely reduce your bandwidth due dominant pole is set by the C=20pF and R=1Mohm. The input impedance will be Rin = Rf/(1+A) and the BW = (1+A)/2.pi.Rf. So, the only way you can improve ur bandwidth is by using the lesser value of Rf. Or what you do to improve your bandwidth and at the same time to achieve high gain is:-

1) Use the RGC(regulated cascode) or common gate configuration as this will isolate 20pF caps from you bandwidth determination
2) Keep the same configuration as yours, but reduce the value of 1Mohm to have a suffucient bandwidth then, add another stage of gain. So, in this way you can achieve high gain and boost the bandwith as well.

Hope this helps you.

 

[archiees]

Thanks Suria,
I want to try the folded cascode. I read few things about folded cascode however, it is still not clear how it wld isolate the input capacitance in BW determination - for my TIA.
Please if you have a reference to any article/books.
PS: My signal frequencies of interest are 10 KHz - 10MHz