Kickback in a sample and hold

[E-goe]

Hi,

Let me describe my problem:

2 basic sample and hold stages ( driver-switch-sample cap ) are cascaded. The first sample and hold cap is sampled first and the switch to the other sample and hold at that time is open ( not conducting ).
After that the switch of the first sample and hold is openend ( some charge injection canbe observed ).
After that ( using non-overlapping clocks in this system ) the switch to the second sample and hold is closed. At that moment a kickback of around 3mV is observed on the first sample and hold cap....

As the first cap is not driven at that point this will gives some errors, while sampling this value to the second sample and holds.

Can anyone suggest me some hints to reduce this kickback?
Can it be caused by the fact that the capacitance between the in and output of the amplifier is to bog? ( for the moment I'm only simulating at schematic level though ). Would it make sense to add some capacitance at the common source point of the differential input pair to increase the capicatance over there.

Does anyone has some good references ( courses/books ) about kickback ?

The amplifiers I use are folded cascodes:

Any feedback is welcome.

Thanks
E-goe

 

[erikl]

...
Does anyone has some good references ( courses/books ) about kickback ?
...
Thanks
E-goe

Chap. 12 of Behzad Razavi's book on "Design of Analog CMOS Integrated Circuits" presents quite a good overview over Switched Capacitor Circuits and their problems. Your "kickback" there is handled as "Channel Charge Injection" and "Clock Feedthrough", and some cancellation methods are shown. An excellent book on Analog CMOS design anyway!

HTH, erikl

 

[lladnar23]

You need to look carefully at bottom-plate sampling, and decide on a good way to sample your 2 SHAs. The quantity you are interested in is the *charge*, so if you sample correctly, voltage kickback won't matter, as long as the charge is accurately sampled.