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Keep Combinational Timing Loop which is disabled by DC compiler

sami154

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Hello Everyone,

I am trying to implement a ring oscillator true random number generator (RO-TRNG) and synthesize it in DC compiler. However, DC compiler is showing me a warning "
Disabling timing arc between pins 'IN2' and 'QN' on cell 'loop[5].ro1/nand_2/U1' to break a timing loop. (OPT-314)". So I am guessing that DC compiler has removed the feedback path from the netlist. But I want to keep the feedback path of the ring oscillator. Can you please let me know how I can keep the combinational loop of the ring oscillator in DC compiler? I have implemented the RTL design in FPGA board using ALLOW_COMBINATORIAL_LOOPS true constraint in vivado and works fine. Now I need your suggestion how I can do the synthesis in DC compiler.

Thanks in advance for your help.
 

BradtheRad

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Does your ring oscillator start up in a defined state or random state?

That is, did you design it so each stage begins in a default state when first powered up? So that the simulator is able to calculate definite values for all nodes and outputs, starting with the first frame of the run?

Try leaving the feedback wire disconnected for the first few cycles, then connect it.
 

ThisIsNotSam

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the problem is that you should not be trying to synthesize in the first place. it is not synchronous logic. it's probably safer to keep it as a blackbox while you synthesize the rest of your circuit
 

SynthWorks

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The message does not mean it "fixed" your timing loop by removing it. It means it is ignoring it because the presence of the timing loop causes the timing tool to be in an infinite loop.
 

Trent_N

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The synthesis is breaking the timing loop, which will not create problems. But, you should not let the synthesis tool touch your ring oscillator. The tool will remove your delay gates and maybe more.
 

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