Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Jitter (pvt sensitivity) of buffer line.

Status
Not open for further replies.

JuliaJ

Newbie level 3
Joined
Oct 29, 2009
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Location
Austin, Texas
Activity points
1,297
On a clock path I had to use buffer insertion technique to achieve specific delay. How can I estimate the additional jitter these buffers give to the signal? In general, from your experience with TSMC 65 G, what variation every clock-type buffer can cause?

Thanks.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top