LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE work.config_package.ALL;
ENTITY top_entity IS
PORT(
SYSCLK : IN std_logic;
CLKOUT : OUT std_logic;
SOD : OUT std_logic_vector(73 DOWNTO 0);
ds : IN std_logic_vector(5 downto 0)
);
END ENTITY top_entity;
ARCHITECTURE rtl OF top_entity IS
SIGNAL osc, clk_160m, clk_50m, clk_i, rst_i, clken_1MHz, clken_1kHz, led : std_logic;
COMPONENT ECP5PLL IS
PORT(CLKI : IN std_logic;
CLKOP : OUT std_logic;
CLKOS : OUT std_logic
);
END COMPONENT ECP5PLL;
COMPONENT OSCG
GENERIC (
DIV : Integer := 128 );
PORT (
OSC : OUT std_logic := 'X' );
END COMPONENT;
COMPONENT powerup_rst IS
GENERIC(
rst_time : IN integer := 5000 --100ms
);
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
force_rst : IN std_logic;
rst_o : OUT std_logic;
rst_n_o : OUT std_logic
);
END COMPONENT powerup_rst;
COMPONENT clockdivider_const
GENERIC(
div_value : integer;
reset_on_disable : boolean
);
PORT(
clk_i : IN std_logic;
rst_i : IN std_logic;
enable : IN std_logic;
clk_out_en : OUT std_logic;
clk_out : OUT std_logic
);
END COMPONENT clockdivider_const;
BEGIN
SOD(0) <= led;
SOD(1) <= '1';
SOD(2) <= '0';
SOD(3) <= '1';
SOD(4) <= '0';
SOD(5) <= '1';
SOD(6) <= ds(0);
SOD(7) <= '1';
SOD(9) <= '0';
SOD(10) <= '0';
SOD(11) <= '0';
SOD(12) <= '0';
SOD(13) <= '0';
SOD(14) <= '0';
oscillator : OSCG
GENERIC MAP (
DIV => 32 )
PORT MAP(
OSC => osc
);
ECP5PLL_inst : COMPONENT ECP5PLL
PORT MAP(
CLKI => osc,
CLKOP => clk_i,
CLKOS => clk_50m
);
SOD(15) <= clk_50m;
SOD(SOD'left downto 16) <= (OTHERS => '0');
-- Reset on power up
u1_powerup_rst_inst : powerup_rst
GENERIC MAP(
rst_time => 50
)
PORT MAP(
clk_i => clk_i,
rst_i => '0',
force_rst => '0',
rst_o => rst_i
);
FPGA_INT <= (OTHERS => '0');
CLKOUT <= clk_160m;
-- Clockdivider for 1MHz clock
u1_clockdivider_const_inst : clockdivider_const
GENERIC MAP(
reset_on_disable => true,
div_value => 160
)
PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable => '1',
clk_out => OPEN,
clk_out_en => clken_1MHz
);
-- Clockdivider for 1kHz clock
u2_clockdivider_const_inst : clockdivider_const
GENERIC MAP(
reset_on_disable => true,
div_value => 1000
)
PORT MAP(
clk_i => clken_1MHz,
rst_i => rst_i,
enable => '1',
clk_out => OPEN,
clk_out_en => clken_1kHz
);
u3_clockdivider_const_inst : clockdivider_const
GENERIC MAP(
reset_on_disable => true,
div_value => 1000
)
PORT MAP(
clk_i => clk_i,
rst_i => rst_i,
enable => clken_1kHz,
clk_out => led,
clk_out_en => open
);
END ARCHITECTURE rtl;