liuy1987
Newbie level 4
Hi, I am using Assura to extract layout (pdk: tsmc35). In the layout, I have a transistor with width of 19.5u and finger of 10, the total width is 195u. But in the av_extracted view, I check the property of that transistor, and find its size is w=19.5u and finger=1, m=1. Then i did post-layout simulation with this extracted view, that transistor does function like a 19.5u-wide transistor. Can anyone tell me why? Why a 19.5u, f=10 transistor turn into a 19.5u,f=1 transistor after RCX?
P.S. DRC and LVS both pass.
Thanks in advance,
Yu
P.S. DRC and LVS both pass.
Thanks in advance,
Yu