quan228228
Full Member level 4
combinational loop
I am a junior IC design enigneer.
I read a "Clock Dividers Made Easy", SNUG Boston,2002 and found some issue which i dont understand. Could you help me?
The problme is below:
I really understand the logic function of clock divider by 3. But there is combinatinal loop in the circuit.
I knew we generally avoid combinational loop in circuit. So, Could you explain,
1. Could divider 3 work stable ? If yes, why?
2. how to judge that the combinational loop work well. For ex., there is setup and hold time requirments for sequential circuit.
Thanks!
attached is the paper i mentioned.
I am a junior IC design enigneer.
I read a "Clock Dividers Made Easy", SNUG Boston,2002 and found some issue which i dont understand. Could you help me?
The problme is below:
I really understand the logic function of clock divider by 3. But there is combinatinal loop in the circuit.
I knew we generally avoid combinational loop in circuit. So, Could you explain,
1. Could divider 3 work stable ? If yes, why?
2. how to judge that the combinational loop work well. For ex., there is setup and hold time requirments for sequential circuit.
Thanks!
attached is the paper i mentioned.