EnderW4785
Member level 1
Hello,
For awhile now I've been battling trying to implement LVDS deserialization in my Spartan-6 with some success. I need to achieve bit-clock rates of 650 MHz in the final implementation, although I'm somewhat limited currently by my FPGA Drigmorn3 evaluation board.
I've been trying to implement that LVDS deserialization laid out in XAPP1064 which seems fairly straightforward. If I had access to all of the pins of the FPGA I'd be all done. Unfortunately because of the limitations of the eval board, the clocking pins on the same bank as the LVDS inputs are not avaliable. What I'm wondering is if there is a way to drive a serdes_1_to_n_clk_ddr_s8_diff block with a clock that is on a different half bank. If so, how? I've tried using clock_generator_ddr_s8_diff and I've run into errors including having buffers in series that aren't allowed or that I need to specify the LOC of an IODELAY.
I can provide more clarification as to what pins I'm using and what errors I'm getting but if someone can tell me if this is even possible that would be a great start. Maybe I need to be doing sdr instead of ddr? Or the pll modules?
Thanks,
Scott
For awhile now I've been battling trying to implement LVDS deserialization in my Spartan-6 with some success. I need to achieve bit-clock rates of 650 MHz in the final implementation, although I'm somewhat limited currently by my FPGA Drigmorn3 evaluation board.
I've been trying to implement that LVDS deserialization laid out in XAPP1064 which seems fairly straightforward. If I had access to all of the pins of the FPGA I'd be all done. Unfortunately because of the limitations of the eval board, the clocking pins on the same bank as the LVDS inputs are not avaliable. What I'm wondering is if there is a way to drive a serdes_1_to_n_clk_ddr_s8_diff block with a clock that is on a different half bank. If so, how? I've tried using clock_generator_ddr_s8_diff and I've run into errors including having buffers in series that aren't allowed or that I need to specify the LOC of an IODELAY.
I can provide more clarification as to what pins I'm using and what errors I'm getting but if someone can tell me if this is even possible that would be a great start. Maybe I need to be doing sdr instead of ddr? Or the pll modules?
Thanks,
Scott