i'm somewhat new to digital design. i'm using ISE WebPack 11.1 and a Nexys 2 board (Spartan 3E FPGA) to learn more about digital design and FPGAs in general.
the WebPack can generate a test fixture (at least initial version of it) for a given module.
below is the initial block it generated for me
Code:
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
i can't understand what global reset is? why is it generated?
for the small designs i wrote i used to write the test fixtures as follows:
Code:
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// Wait 100 ns for global reset to finish
#100;
// reset
reset = 1'b1;
// wait for reset to finish
#20;
reset = 1'b0;
// Add stimulus here
end
but then i removed the global reset and wrote the code as follows and my test bench still worked:
Code:
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
// reset
reset = 1'b1;
// wait for reset to finish
#20;
reset = 1'b0;
// Add stimulus here
end
i would appreciate the explanation of what the global reset is. is it needed for the test fixture to settle down or it is just something the generator inserts?