Hi,
I have a simple design and want to optimize it (first preference is area and then speed). so how can ISE help me to find Critical Path in my Design and to resolve them (by setting which constraints). Also guide about Verilog tricks to optimize code.
Also I have microblaze based system (EDK project) as subpart of my design which is taking huge part of my Device. So can I optimize it also?
For EDK part you can open .ngc (in implementation folder) in Floor Planner and choose a smaller place in FPGA for different modules and test if better choice is available for area.